Title :
VLSI implementation of single chip encoder/decoder for low bitrate visual communication
Author :
Miyanohana, Koji ; Fujita, Gen ; Yanagida, Kazuhiro ; Onoye, Takao ; Akawa, Isao Shir
Author_Institution :
Dept. of Inf. Syst. Eng., Osaka Univ., Japan
Abstract :
A single chip encoder and decoder dedicated to the low bitrate visual communication is described, with the main theme focused on the object extraction and vector quantization. A new scheme is devised for a detailed edge detector, which is to seek horizontal and vertical edges simultaneously. A new concept is also introduced into a PE (Processing Element) array so as to be commonly used by the vector quantizer and the motion estimator. Owing to a sophisticated architecture, these CODEC facilities have been implemented in 72.24 mm2 by a 0.6 μm triple-metal CMOS technology, which can enable the visual communication of QCIF (176×144) 10 fps pictures at a bitrate below 30 K bps. The designed encoder and decoder operate at 10.0 MHz, and dissipate 147 mW from a single 3.3 V supply
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; edge detection; motion estimation; vector quantisation; video codecs; visual communication; 0.6 micron; 10.0 MHz; 147 mW; 3.3 V; 30 kbit/s; CODEC; QCIF picture; VLSI; edge detection; low bit-rate visual communication; motion estimation; object extraction; processing element array; single chip encoder/decoder; triple-metal CMOS technology; vector quantization; Bandwidth; Bit rate; CMOS technology; Decoding; Discrete cosine transforms; Optical fiber networks; Standardization; Transform coding; Very large scale integration; Visual communication;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606618