A novel digit-serial systolic array for modular multiplication

In this paper, a novel digit-serial systolic modular multiplier is presented. To the authors´ knowledge, this is the very first digit-serial systolic array for modular multiplication. The proposed architecture is highly regular and modular and thus well suited to VLSI implementation. The important feature of the proposed architecture is that different throughput performances can be easily achieved simply by varying the digit size. If the digit size is chosen appropriately, the proposed digit-serial architecture can meet the throughput requirement of a certain application with minimum hardware. The developed modular multiplier is useful in constructing a systolic RSA cryptosystem, where modular multiplication is the kernel operation