DocumentCode :
2165116
Title :
A new perspective of barrier material evaluation and process optimization
Author :
Zhao, Larry ; Tikei, Z. ; Gischia, G.G. ; Volders, Henny ; Beyer, Gerald
Author_Institution :
Intel Corp., Leuven
fYear :
2009
fDate :
1-3 June 2009
Firstpage :
206
Lastpage :
208
Abstract :
A novel test structure based on a planar capacitor design has been used for advanced barrier material evaluation and process optimization. This structure enables intrinsic reliability study of Cu/low-k interconnects. Various barrier materials such as CuMn self-forming barrier, ALD Ru, and PVD TaNTa on different dielectric films have been investigated to understand their intrinsic limits of barrier performance. The learning generated from the novel test structure has been directly used for barrier optimization of dual damascene processes.
Keywords :
capacitors; dielectric thin films; interconnections; advanced barrier material evaluation; dielectric films; dual damascene processes; intrinsic reliability; planar capacitor design; process optimization; self-forming barrier; Atherosclerosis; Automatic testing; Capacitors; Design optimization; Dielectric films; Dielectric materials; Materials testing; Needles; Passivation; Probes; ALD Ru; CDO; Cu/low-k; CuMn; barrier; interconnect; planar capacitor; reliability; self-forming barrier;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference, 2009. IITC 2009. IEEE International
Conference_Location :
Sapporo, Hokkaido
Print_ISBN :
978-1-4244-4492-2
Electronic_ISBN :
978-1-4244-4493-9
Type :
conf
DOI :
10.1109/IITC.2009.5090389
Filename :
5090389
Link To Document :
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