Title :
New trends in wafer level packaging
Author :
Sillon, N. ; Henry, D. ; Souriau, J.-C. ; Brun, J. ; Boutry, H. ; Cheramy, S.
Author_Institution :
CEA-Leti Minatec, Grenoble
Abstract :
We present in this paper the two generic integration schemes developed at Leti, aiming to address two opposite industrial needs. The first scheme, based on TSV free via belt technology, allows wafer level integration of highly heterogeneous systems taking into account different technologies, wafer and die sizes and mainly targets end-user companies looking for generic technologies. The second one, based on TSV WLP and active silicon interposer, mainly addresses the IDMs needs. Main technological bricks related to both schemes are presented and validated through specific demonstrators.
Keywords :
wafer level packaging; TSV WLP; active silicon interposer; die sizes; generic integration schemes; heterogeneous systems; via belt technology; wafer level packaging; Wafer scale integration;
Conference_Titel :
Interconnect Technology Conference, 2009. IITC 2009. IEEE International
Conference_Location :
Sapporo, Hokkaido
Print_ISBN :
978-1-4244-4492-2
Electronic_ISBN :
978-1-4244-4493-9
DOI :
10.1109/IITC.2009.5090390
