Author :
Parihar, S. ; Angyal, M. ; Boeck, B. ; Reber, D. ; Singhal, A. ; Van Gompel, T. ; Li, R. ; Wilson, B. ; Wright, M. ; Chen, J. ; Grudowski, P. ; Jeon, Y. ; Qi, W. ; Bai, X. ; Parker, L. ; Strozewski, K. ; Smith, D. ; Roling, S. ; Sparks, T. ; Stephens, T.
Author_Institution :
Motorola Digital DNA Labs. & AMD Technol. Dev. Group, Austin, TX, USA
Abstract :
In this work components of the next generation 0.10 /spl mu/m CMOS technology are presented. They form the core of a platform encompassing logic, non volatile memory, and analog blocks. High performance bulk devices use 18 /spl Aring/ gate oxide (24 /spl Aring/ inversion Tox) while low power devices use 25 /spl Aring/ gate oxide (31 /spl Aring/ inversion Tox) for reduced gate leakage. Gate lengths range from 65 nm for the high performance devices to 90 nm for the low power devices. Both 3.3 V and 2.5 V I/Os are supported using 70 /spl Aring/ and 50 /spl Aring/ oxide devices. The backend employs low-k (k/spl sim/3) dielectric with multiple levels of Cu metallization. The high density 6T SRAM cell size is 1.33 /spl mu/m/sup 2/.
Keywords :
CMOS integrated circuits; SRAM chips; copper; dielectric thin films; integrated circuit interconnections; integrated circuit technology; low-power electronics; 0.10 micron; 2.5 V; 3.3 V; CMOS technology; analog block; backend process; bulk device; copper interconnect; gate leakage; gate oxide; high density 6T SRAM cell; high performance device; logic block; low K dielectric; low power device; multilevel metallization; nonvolatile memory block; CMOS logic circuits; CMOS technology; Copper; Dielectric substrates; Etching; Isolation technology; Lithography; Radio frequency; Random access memory; Space technology;
