An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

Author

Thompson, S. ; Alavi, M. ; Arghavani, R. ; Brand, A. ; Bigwood, R. ; Brandenburg, J. ; Crew, B. ; Dubin, V. ; Hussein, M. ; Jacob, P. ; Kenyon, C. ; Lee, E. ; Mcintyre, B. ; Ma, Z. ; Moon, P. ; Nguyen, P. ; Prince, M. ; Schweinfurth, R. ; Sivakumar, S. ;

Author_Institution

Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA

fYear

2001

fDate

2-5 Dec. 2001

Abstract

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance operation from 0.7 to 1.4 V, and a 5% linear shrink to reduce the 6-T SRAM cell to 2.00 /spl mu/m/sup 2/ while still using 248 nm lithography. Saturation drive currents of 1.30 mA//spl mu/m for N-channel and 0.66 mA//spl mu/m for P-channel low VT devices are the highest reported to date. Excellent device short channel effects are obtained for the 60 nm gate length devices as measured by the 270 mV threshold voltage and <100 mV/V DIBL. These results have been achieved on both 200 and 300 mm wafers.

Keywords

CMOS digital integrated circuits; CMOS logic circuits; SRAM chips; circuit optimisation; integrated circuit technology; low-power electronics; microprocessor chips; 0.7 to 1.4 V; 130 nm; 130 nm generation logic technology; 200 mm; 200 mm wafers; 248 nm; 248 nm lithography; 270 mV; 300 mm; 300 mm wafers; 6-T SRAM device matching; 60 nm; 60 nm gate dimension transistors; CMOS SRAM; CMOS logic technology; CMOS microprocessor; Cu interconnects; DIBL; N-channel devices; P-channel devices; SRAM cell size; drive current; high performance operation; high performance optimization; linear shrink; low power operation; saturation drive currents; short channel effects; threshold voltage; CMOS technology; Isolation technology; Jacobian matrices; Lithography; Logic; Moon; Random access memory; Threshold voltage; Transistors; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979479

Filename

979479