DocumentCode
2165493
Title
Redeeming IPC as a performance metric for multithreaded programs
Author
Lepak, Kevin M. ; Cain, Harold W. ; Lipasti, Mikko H.
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear
2003
fDate
27 Sept.-1 Oct. 2003
Firstpage
232
Lastpage
243
Abstract
Recent work has shown that multithreaded workloads running in execution-driven, full-system simulation environments cannot use instructions per cycle (IPC) as a valid performance metric due to nondeterministic program behavior. Unfortunately, invalidating IPC as a performance metric introduces its own host of difficulties: special workload setup, consideration of cold-start and end-effects, statistical methodologies leading to increased simulation bandwidth, and workload-specific, higher-level metrics to measure performance. We explore the nondeterminism problem in multithreaded programs, describe a method to eliminate nondeterminism across simulations of different experimental machine models, and demonstrates the suitability of this methodology for performing architectural performance analysis, thus redeeming IPC as a performance metric for multithreaded programs.
Keywords
digital simulation; multi-threading; multiprogramming; parallel architectures; parallel machines; pipeline processing; program diagnostics; IPC; architectural performance analysis; execution-driven simulation; instructions per cycle; machine models; multithreaded programs; nondeterministic program behavior; performance metric; Acceleration; Analytical models; Computational modeling; Computer aided instruction; Computer simulation; Delay; Measurement; Multiprocessing systems; Operating systems; Statistical analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures and Compilation Techniques, 2003. PACT 2003. Proceedings. 12th International Conference on
ISSN
1089-795X
Print_ISBN
0-7695-2021-9
Type
conf
DOI
10.1109/PACT.2003.1238019
Filename
1238019
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