DocumentCode
2165587
Title
Circuit design for current-sensing completion detection
Author
Lampinen, Harri ; Vainio, Olli
Author_Institution
Signal Process. Lab., Tampere Univ. of Technol., Finland
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
185
Abstract
Circuit techniques for current-sensing completion detection (CSCD) are developed and evaluated. CSCD is a mixed analog-digital method for detecting the completion of operations in digital CMOS. The technique is therefore well suited for controlling self-timed asynchronous digital VLSI circuits. Design of an experimental CSCD chip including digital arithmetic is discussed and the performance of the chip is characterized
Keywords
CMOS logic circuits; VLSI; asynchronous circuits; digital arithmetic; logic testing; VLSI; current-sensing completion detection; digital CMOS; digital arithmetic; mixed analog-digital method; self-timed asynchronous circuits; Circuit synthesis; Current measurement; Diodes; Encoding; Logic; Power supplies; Resistors; Semiconductor device measurement; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706872
Filename
706872
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