DocumentCode
2166044
Title
An Enhanced Logic BIST Architecture for Online Testing
Author
Yang, F. ; Chakravarty, S. ; Devta-Prasanna, N. ; Reddy, S.M. ; Pomeranz, I.
Author_Institution
Univ. of Iowa, Iowa City, IA
fYear
2008
fDate
7-9 July 2008
Firstpage
10
Lastpage
15
Abstract
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture to detect such defects is proposed. Unlike other sequences, like checking experiments, the enhancements are simple and independent of the circuit under test.
Keywords
built-in self test; logic testing; built-in self test; logic BIST architecture; online testing; Built-in self-test; Circuit faults; Circuit testing; Cities and towns; Clocks; Electrical fault detection; Fault detection; Flip-flops; Logic circuits; Logic testing; Flush Test; Logic BIST; Online Testing; Stuck-open Faults;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
Conference_Location
Rhodes
Print_ISBN
978-0-7695-3264-6
Type
conf
DOI
10.1109/IOLTS.2008.48
Filename
4567053
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