DocumentCode
2166105
Title
Physical Demonstration of Polymorphic Self-Checking Circuits
Author
Ruzicka, Richard ; Sekanina, Lukas ; Prokop, Roman
Author_Institution
Fac. of Inf. Technol., Brno Univ. of Technol., Brno
fYear
2008
fDate
7-9 July 2008
Firstpage
31
Lastpage
36
Abstract
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized in a self-checking polymorphic adder. This paper presents an experimental evaluation of this novel implementation.
Keywords
adders; logic gates; logic functions; polymorphic NAND gate; polymorphic NOR gate; polymorphic gates; polymorphic self-checking circuits; reconfigurable technology; self-checking polymorphic adder; Adders; Automatic testing; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Logic functions; Logic testing; Power supplies; Voltage control; polymorphic electronics; polymorphic gates; self-checking circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
Conference_Location
Rhodes
Print_ISBN
978-0-7695-3264-6
Type
conf
DOI
10.1109/IOLTS.2008.23
Filename
4567056
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