Author :
Kim, D.-C. ; Park, S.K. ; Hong, H.S. ; Kim, I.G. ; Kim, Y.T. ; Kim, Y.B. ; Kim, H.S. ; Park, H.S. ; Nam, M.H. ; Suh, M.S. ; Nam, K.B. ; Lee, J.S. ; Kim, N.S. ; Lee, T.K. ; Kim, J.Y. ; Lee, S.H. ; Lee, B.C. ; Kwon, H.Y. ; Choi, J.H. ; Om, J.C. ; Wi, B.R. ;
Author_Institution :
Memory R&D Div., Hynix Semicond. Co. Ltd, Kyoungki, South Korea
Abstract :
In this paper, we intensively investigated the influence of thermally induced stress by rapid thermal annealing (RTA) on DRAM data retention time. Methods of reducing thermal stress induced by RTA and the optimum location of RTA (to suppress tDPL fail) were proposed through our extensive experimental results. Low temperature (below 800/spl deg/C) BPSG flow annealing following RTA after capacitor formation eliminated the residual stress, and resulted in dramatically improved data retention time characteristics by 120%. By adoption of thin buffer oxide (/spl sim/100 /spl Aring/) under gate spacer SiN film, we solved the problem of hot carrier degradation of cell transistor by reduced trap sites by virtue of the stress-buffering role, and additionally improved data retention time by 60%.
Keywords :
CMOS memory circuits; DRAM chips; hot carriers; integrated circuit reliability; internal stresses; rapid thermal annealing; stress relaxation; thermal stresses; 1 Gbit; 100 angstrom; 1Gb DRAM technology; 256 Mb DRAM technology; 256 Mbit; 800 C; B2O3-P2O5-SiO2; BPSG; RTA; SiO/sub 2/-SiN; capacitor formation; data retention time; data-in to pre-charge time failure rate; gate spacer SiN film; hot carrier degradation; low temperature BPSG flow annealing; optimum RTA location; rapid thermal annealing; residual stress elimination; stress relaxation; stress-buffering role; thermal stress reduction; thermally induced stress; thermally induced stress relief; thin buffer oxide; trap sites; Capacitance; Capacitors; Contact resistance; Doping; Random access memory; Rapid thermal annealing; Residual stresses; Temperature; Thermal resistance; Thermal stresses;
