Layout, design finish and packaging of a redundant signal multiprocessor architecture with WSI dimensions

An ASIC (application specific integrated circuit) design flow for the realization of a multiprocessor structure has been successfully established and verified. This design flow includes standard tools and project-specific extensions, especially for verification tasks and preparation of WSI (wafer scale integration) data fractioning. The achieved layout and factory finishing method `nonoverlapping hierarchy´ uses the regular multiproject wafer approach of an ASIC direct-write E-beam foundry and seems to have no area limits within the available wafer dimensions. Due to the extensive utilization of standard tools and flows wherever possible, a fast design and fabrication process for prototypes is guaranteed. This leads to a minimization of manpower, time, and processing costs