Soft Error Rates of Hardened Sequentials utilizing Local Redundancy

Process scaling is well know to increase overall chip-level soft error rates (SER) if no additional mitigation techniques are applied [Seifert04]. The purpose of this study is to summarize recent investigations conducted by the author to characterize the SER benefits and limitations of one particular SER mitigation technique: radiation hardened sequentials that utilize local redundancy. The studied devices include several flavors of single-event upset tolerant sequentials (SEUT [Hazucha04]) which is an interlocked device similar to DICE (dual interlocked CEII [Calin96]) and built-in soft error resilient devices (BISER [Mitra05, Zhang04]) which block rather than correct single event upsets (SEU). Redundancy based hardened sequential designs discussed in this work can only recover single node upsets, i.e. from particle strikes where only one node collects significant amounts of charge. It is therefore crucial to separate "critical nodes" in space to minimize the amount of charge collected at more than one node, i.e. minimize "charge sharing". A second major upset mechanisms of the studied sequentials are clock node strikes [Seifert07]. Please note that this upset mechanism does not involve charge sharing and therefore is expected to be a significant SER contributor unless the clock tree has been hardened. Finally for non error blocking schemes and single node strikes that yield transient glitches only, pulses can propagate and could be potentially latched by downstream sequentials, similar to noise in combinational logic. This soft error contribution component of radhard sequentials is neglected in this study, where solely static failure rates of radhard devices have been investigated. Neutron- and alpha-particle induced upset rates of SEUT and of BISER devices have been collected as a function of voltage and data pattern. All investigated designs have been implemented using test-chips built in a 45 nm high-k + metal gate process [Mistry07]. Neutron characterization w- - as performed at the Los Alamos National Laboratory (LANSCE), whereas alpha-particle irradiation was conducted in-house using Thorium-232 foils. By careful selection of data patterns and designs with different critical node distances, the impact of the above discussed upset mechanisms have been separated and quantified. Our results highlight that soft error reduction values in excess of 100times with respect to non- hardened designs are feasible in 45nm technologies. Without proper clock protection, SER benefits are limited to about 10-30times, however. Further, if no attention is given to proper separation of critical nodes, upset rates similar to those of non-radhard devices can be expected. Despite the encouraging result that two orders of magnitude reduction in nominal SER is feasible in 45 nm technologies, our results also project that compact redundancy hardened designs will have soft error rates similar to non-hardened designs within a few technology generations if no additional mitigation techniques are applied to reduce the impact of charge sharing.