Triple-self-aligned, planar double-gate MOSFETs: devices and circuits

Author

Guarini, K.W. ; Solomon, P.M. ; Zhang, Y. ; Chan, K.K. ; Jones, E.C. ; Cohen, G.M. ; Krasnoperova, A. ; Ronay, M. ; Dokumaci, O. ; Bucchignano, J.J. ; Cabral, C., Jr. ; Lavoie, C. ; Ku, V. ; Boyd, D.C. ; Petrarca, K.S. ; Babich, I.V. ; Treichler, J. ; Koz

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2001

fDate

2-5 Dec. 2001

Abstract

We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.

Keywords

CMOS logic circuits; MOSFET; chemical mechanical polishing; electron beam lithography; passivation; photolithography; wafer bonding; NOR logic; PAGODA; back gate undercut; double-gate FET operation; front-end CMP; interface transport; inverter action; mixed optical/e-beam lithography; passivation; silicided silicon source/drain sidewalls; triple-self-aligned planar double-gate MOSFETs; wafer bonding; Double-gate FETs; Inverters; Lithography; Logic devices; MOSFETs; Optical device fabrication; Optical devices; Passivation; Silicon; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979527

Filename

979527