A single chip DVB receiver for variable-rate QPSK demodulation and forward error correction

This paper describes a single chip DVB compliant receiver that integrates a variable rate QPSK demodulator with a Viterbi decoder, de-interleaver, and a Reed-Solomon decoder. Using a fixed rate sampling clock it handles continuously variable symbol rate from 1 Msps to 45 Msps. Careful floor planning and flat place and route squeezed the 116,000 nand-equivalent gate design into an area of 38.8 mm². It has been fabricated with a 0.5 μm CMOS TLM process. It has been extensively tested in a real-world set-up and proved fully functional