Dynamic reconfigurable implementations of AES algorithm based on pipeline and parallel structure

This paper analyzes algorithmic characteristics of AES Encryption/Decryption, and proposes a design methodology for AES algorithm digital hardware circuit through integrating the technologies of pipeline and parallel connections with dynamic reconfiguration. And a dynamic reconfiguration circuit model was built to test out the design methodology. The results of simulation and verification experiments prove that this model highlights all the advantages of dynamic reconfiguration technology, considers the application of parallel connections, increases the throughput, and excels in processing speed. Thus it illustrates a good and prospect of application and extension.