Title :
Breakdown analysis in JI, SOI and partial SOI power structures
Author :
Udrea, F. ; Popescu, A. ; Milne, W.
Author_Institution :
Dept. of Eng., Cambridge Univ., UK
Abstract :
Summary form only given. SOI could be the future technology for power devices and integrated circuits. Unlike the conventional Junction Isolation (JI) technology, SOI benefits from simple and effective isolation, low leakage currents, reduced interference between low voltage and high voltage components and very high speed. SOI may, however, suffer from low breakdown voltage, self-heating and latch-up. These are essential aspects, especially for high power applications, where high currents and high voltages are required. The key issue in building a Power Integrated Circuit (PIC) based on SOI is an efficient Resurf (REduced SURface Field) effect to ensure a high breakdown voltage. This may be achieved by using a thick oxide layer and a top field oxide. However, thick oxide layers may cause high temperatures to be developed in the circuit. At the same time the final breakdown voltage is still below that of an optimised JI structure. New partial SOI device structures are proposed and demonstrated through numerical simulations. It is shown that the partial SOI technology solves one of the major problems of conventional SOI technology, the reduced breakdown voltage, with little compromise in the switching speed and device isolation. Extensive two-dimensional analyses and analytical modelling of the breakdown behaviour in JI, SOI and partial SOI have been carried out. The results indicate that partial SOI technology could be a serious alternative to conventional SOI for PICs
Keywords :
electric breakdown; isolation technology; leakage currents; power integrated circuits; power semiconductor diodes; power transistors; silicon-on-insulator; Resurf effect; SOI power structures; Si; analytical modelling; breakdown voltage; device isolation; junction isolation technology; latch-up; leakage currents; numerical simulations; partial SOI power structures; power integrated circuit; reduced surface field effect; self-heating; thick oxide layer; top field oxide; Analytical models; Electric breakdown; Integrated circuit technology; Interference; Isolation technology; Leakage current; Low voltage; Numerical simulation; Power integrated circuits; Temperature;
Conference_Titel :
SOI Conference, 1997. Proceedings., 1997 IEEE International
Conference_Location :
Fish Camp, CA
Print_ISBN :
0-7803-3938-X
DOI :
10.1109/SOI.1997.634953