DocumentCode :
2166489
Title :
Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs
Author :
Uemura, Taiki ; Tanabe, Ryo ; Tosaka, Yoshiharu ; Satoh, Shigeo
Author_Institution :
Fujitsu Labs. Ltd., Tokyo
fYear :
2008
fDate :
7-9 July 2008
Firstpage :
117
Lastpage :
122
Abstract :
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We proposed a flip-flop of SET-SEU-RHBD. This flip-flop has LPF using a C-element with dual transmission and applies an MNL technique only on the master latch. This flip-flop is designed with 45-nm technology and a 16-grid height. Mitigation efficiencies of the flip-flop are estimated by accelerated experiments and simulations. The flip-flop can protect 90% of SEU and 52 ps SET pulse with low penalties.
Keywords :
flip-flops; large scale integration; logic circuits; low-pass filters; dual transmission; flip-flop; low-pass filters; mitigation techniques; radiation hardened by design; sequential logic; single-event transients; single-event upsets; Combinational circuits; Error correction codes; Flip-flops; Latches; Logic circuits; Logic devices; Logic testing; Low pass filters; Radiation hardening; Single event upset; LPF; RHBD; SET; SEU; Soft error;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
Conference_Location :
Rhodes
Print_ISBN :
978-0-7695-3264-6
Type :
conf
DOI :
10.1109/IOLTS.2008.28
Filename :
4567072
Link To Document :
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