Title :
A Modular Memory BIST for Optimized Memory Repair
Author :
Oehler, P. ; Bosio, Alberto ; Natale, Giorgio Di ; Hellebrand, Sybille
Author_Institution :
Univ. of Paderborn, Paderborn
Abstract :
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions reuse IP-Cores for BIST without modifications. However, this prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced, which supports a more efficient interleaving of test and repair and can be achieved with only small modifications in the BIST control.
Keywords :
built-in self test; integrated circuit testing; system-on-chip; SoC; built-in self-repair solutions; memory test; modular memory BIST; on-chip infrastructure; optimized memory repair; reuse IP-cores; Binary trees; Built-in self-test; Fault detection; Hardware; Information retrieval; Intellectual property; Interleaved codes; Manufacturing; System-on-a-chip; Testing;
Conference_Titel :
On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
Conference_Location :
Rhodes
Print_ISBN :
978-0-7695-3264-6
DOI :
10.1109/IOLTS.2008.30
