Title :
Shared tag for MMU and cache memory
Author :
Lee, Yonghwan ; Jeong, Wookyung ; Ahn, Sangjun ; Lee, Yongsurk
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
In this paper, we propose a shared tag memory through which both TLB and cache memory can be accessed. The shared tag architecture reduces the area of conventional cache tag memory and also improves the speed of cache system. To validate the proposed architecture, we conducted trace-driven simulations and measured the area and speed based on VLSI circuits
Keywords :
VLSI; buffer storage; cache storage; integrated memory circuits; memory architecture; shared memory systems; MMU; TLB; VLSI circuit; cache memory; shared tag architecture; trace-driven simulation; Area measurement; Cache memory; Circuit simulation; Frequency; Integrated circuit measurements; Microprocessors; Semiconductor device measurement; Technical Activities Guide -TAG; Velocity measurement; Very large scale integration;
Conference_Titel :
Semiconductor Conference, 1997. CAS '97 Proceedings., 1997 International
Conference_Location :
Sinaia
Print_ISBN :
0-7803-3804-9
DOI :
10.1109/SMICND.1997.651553
