DocumentCode :
2166839
Title :
Basic Architecture for Logic Self Repair
Author :
Koal, Tobias ; Vierhaus, Heinrich T.
Author_Institution :
Comput. Eng. Group, Brandenburg Univ. of Technol., Cottbus
fYear :
2008
fDate :
7-9 July 2008
Firstpage :
177
Lastpage :
178
Abstract :
Built-in self test (BIST) and built-in self repair (BISR) techniques have been developed for memory blocks in recent years. Such techniques are suited to enhance production yield, but also to facilitate long-term dependable circuits though self repair in the field of application. BISR for logic circuits has shown to be much more complex, for which only a few approaches have been published so far. However, the roadmap of semiconductor industries sees a requirement of such technology by about 2012. This paper introduces a basic BISR methodology for logic circuits.
Keywords :
built-in self test; logic testing; BISR techniques; BIST techniques; built-in self repair; built-in self test; logic circuits; logic self repair; memory blocks; semiconductor industries; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electronics industry; Field programmable gate arrays; Logic circuits; Logic testing; Production; Programmable logic arrays; BISR; logic selfrepair;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
Conference_Location :
Rhodes
Print_ISBN :
978-0-7695-3264-6
Type :
conf
DOI :
10.1109/IOLTS.2008.17
Filename :
4567086
Link To Document :
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