• DocumentCode
    2166895
  • Title

    Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448

  • Author

    Pignol, Michel ; Parrain, Thierry ; Claverie, Vincent ; Boleat, C. ; Estaves, Guy

  • Author_Institution
    CNES, Toulouse
  • fYear
    2008
  • fDate
    7-9 July 2008
  • Firstpage
    182
  • Lastpage
    184
  • Abstract
    The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with ´light´ features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this paper.
  • Keywords
    fault tolerance; microprocessor chips; silicon-on-insulator; DT2 fault-tolerant architectures; PowerPC7448 microprocessor; SOI; TAFT fault tolerance; duplex multiplexed in time; space community; Actuators; Computer architecture; Costs; Fault detection; Fault tolerance; Field programmable gate arrays; Microprocessors; OFDM modulation; Space technology; Testing; COTS components; DMT; DST; DT2; PowerPC7448; fault tolerance; space applications; testbench;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
  • Conference_Location
    Rhodes
  • Print_ISBN
    978-0-7695-3264-6
  • Type

    conf

  • DOI
    10.1109/IOLTS.2008.24
  • Filename
    4567088
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2166895