Title :
An integrated functional tester for CMOS logic
Author :
Low, William ; Ivanov, André
Author_Institution :
Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
Abstract :
This paper presents the architecture of a functional tester system based on a functional tester chip (FTC) featuring per-pin programmability, output waveform formatting (NR, RC, RH, and RL), input window comparison and on-the-fly format switching. Waveforms are encoded using a set of simple 8-bit instructions. The bandwidth requirements of each channel is 8 bits per test vector. A four-channel FTC implemented using digital standard cells, with a 1.2 micron dual metal layer CMOS process, has a die size of 7×6 mm2 (core: 6×5 mm 2). Each channel occupies approximately 17% of the core area. Almost half the channel area is used by the format memory which provides a cache of the required timing and formats for a given test. Preliminary results based on measurements from an early version of the wave formatting circuit suggest that edge resolutions of at least 1.5 ns are possible
Keywords :
CMOS integrated circuits; encoding; functional analysis; integrated circuit testing; logic testing; 1.2 mum; 5 mm; 6 mm; 7 mm; 8-bit instructions; CMOS logic; bandwidth requirements; die size; digital standard cells; dual metal layer CMOS process; edge resolutions; encoded; format memory; functional tester chip; functional tester system; input window comparison; integrated circuit testing; integrated functional tester; on-the-fly format switching; output waveform formatting; programmability; required timing; test vector; wave formatting circuit; Bit rate; CMOS logic circuits; CMOS process; Circuit testing; Integrated circuit measurements; Integrated circuit testing; Logic testing; Prototypes; System testing; Timing;
Conference_Titel :
Electrical and Computer Engineering, 1993. Canadian Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-2416-1
DOI :
10.1109/CCECE.1993.332196
