Title :
On fault coverage in VLSI built-in self-test with multiple intermediate signature analysis
Author :
Zhang, Chun ; Wu, Yuejian ; Ivanov, Andr
Author_Institution :
Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
Abstract :
This paper studies the fault coverage performance with multiple intermediate signature analysis. Two fault coverage models are presented. Unlike the results reported in the literature, these models reveal that the fault coverage with multiple intermediate signature analysis depends on the times when the signatures are checked. Experimental results on benchmark circuits are reported
Keywords :
VLSI; built-in self test; integrated circuit testing; logic testing; VLSI built-in self-test; benchmark circuits; fault coverage; fault coverage models; fault coverage performance; multiple intermediate signature analysis; signatures check times; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Signal analysis; Test pattern generators; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 1993. Canadian Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-2416-1
DOI :
10.1109/CCECE.1993.332197
