Title :
A new multiple transistor parameter design methodology for high speed low power SoCs
Author :
Takeuchi, K. ; Mogami, T.
Author_Institution :
Silicon Syst. Res. Labs, NEC, Kanagawa, Japan
Abstract :
A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple V/sub TH/, V/sub DD/, and T/sub OX/, for System-on-a-Chip´s (SoC´s) is proposed. Reasonable optimization results are automatically obtained for various SoC configurations, which is difficult to achieve intuitively. It was found that the MP design is particularly effective for SoC´s consisting of circuit blocks with different speed requirements.
Keywords :
circuit optimisation; high-speed integrated circuits; integrated circuit design; low-power electronics; energy-delay concept; high-speed low-power system-on-a-chip; multiple blocks optimization; multiple transistor parameter design methodology; Circuits; Clocks; Delay; Design methodology; Design optimization; Low voltage; National electric code; Performance evaluation; Silicon; System-on-a-chip;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979558
