A new multiple transistor parameter design methodology for high speed low power SoCs

A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple V/sub TH/, V/sub DD/, and T/sub OX/, for System-on-a-Chip´s (SoC´s) is proposed. Reasonable optimization results are automatically obtained for various SoC configurations, which is difficult to achieve intuitively. It was found that the MP design is particularly effective for SoC´s consisting of circuit blocks with different speed requirements.