Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips

The downsizing of transistor dimensions enabled in the future nanotechnologies will inevitably increase the number of faults in the complex ULSI chips. To maintain the production yield at acceptable level, several levels of protection mechanisms will have to be implemented to tolerate the permanent and transient faults occurring in the physical layers. In this paper, we study fault tolerance at the architectural level in multiport processor grids (MPG) through core dual diagnosis and self-configuration of communications. MPGs are considered to ensure the scalability of future hundred-core chips. We characterize defective technologies by the IOP reachability (i.e., the ability of the IOPs to contact a fraction of cores in the grid) that we study as a function of the fraction of defective cores or links. We show that almost all valid cores in the grid are accessible by all input-output ports (IOP) up to approximately 20-25% of defective cores. This property is quasi-independent of the position of the IOPs in the grid.