DocumentCode
2167302
Title
A Low-Cost Accumulator-Based Test Pattern Generation Architecture
Author
Magos, D. ; Voyiatzis, I. ; Tarnick, S.
Author_Institution
Dept. of Inf., Technol. Educ. Inst. of Athens, Athens
fYear
2008
fDate
7-9 July 2008
Firstpage
267
Lastpage
272
Abstract
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding approaches for accumulator-based test generation.
Keywords
automatic test pattern generation; decoding; integrated circuit testing; accumulator-based test pattern generation architecture; decoder; external tester; test-time reduction; Automatic testing; Benchmark testing; Boolean functions; Circuit testing; Data structures; Hardware; Switches; System testing; Test pattern generators; Traveling salesman problems; Accumulator-based test-pattern generation; Built-In Self Test; Test-set embedding;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
Conference_Location
Rhodes
Print_ISBN
978-0-7695-3264-6
Type
conf
DOI
10.1109/IOLTS.2008.54
Filename
4567105
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