Title :
Overcoming Cu/CVD low-k integration challenges in a high performance interconnect technology
Author :
Lytle, S.A. ; Karthikeyan, S. ; Oladeji, I.O. ; Lee, T.J. ; Li, H.M. ; Zhang, A. ; Steiner, K.G. ; Merchant, S.M. ; Oh, M. ; Jessen, S.W. ; Gibson, G.W., Jr. ; Ramappa, D. ; Taylor, J.A. ; Tse, T.Y. ; Hariharaputhiran, M. ; Hua, G. ; Kim, H.T. ; Mattern,
Author_Institution :
Agere Syst., Orlando, FL, USA
Abstract :
In this paper we describe how several challenges have been overcome in the integration of a high performance, manufacturable, Cu/CVD low-k (Coral) 0.13 /spl mu/m interconnect technology. Specifically, we discuss solving issues with 193 nm lithography for M1 using different hardmask schemes, and the challenges of 248 nm trench resist poisoning due to N-H evolution from open vias in a full via first dual damascene scheme. Optimization of the dual damascene dielectric stack and Cu CMP with regard to reliability concerns are also elucidated. Yield and reliability data are provided that demonstrate the manufacturability of the integration solutions that are discussed.
Keywords :
CVD coatings; chemical mechanical polishing; copper; dielectric thin films; integrated circuit interconnections; integrated circuit reliability; integrated circuit yield; masks; photoresists; ultraviolet lithography; 0.13 micron; 193 nm; 248 nm; CMP; Coral; Cu; Cu/CVD low-k dielectric integration; DUV lithography; dual damascene processing; hardmask; interconnect technology; manufacturability; open via; reliability; trench resist poisoning; yield; Copper; Dielectric materials; Etching; Integrated circuit interconnections; Integrated circuit technology; Lithography; Random access memory; Resists; Semiconductor device manufacture; Silicon carbide;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979579
