Real impact of W/WNx/Poly-Si gate stack in volume production of high density DRAM

Author

Il-Gweon Kim ; Nam-Sung Kim ; Jun-Ho Choy ; Byung-Hak Lee ; Yong-Gue Sung ; Jong-Hwan Kim ; Jin-Hee Cho ; Dong-Chan Kim ; Kee-Soo Kim ; Jo-Bong Choi ; Se-Kyoung Choi ; Young-Woo Kweon ; Ho-Yup Kwon ; Dae-Guy Park ; Joo-Seog Park ; Dae-Young Park

Author_Institution

Memory R&D Div., Hynix Semicond. Inc, Cheongju, South Korea

fYear

2001

fDate

2-5 Dec. 2001

Abstract

We have investigated the feasibility for volume production of high density DRAMs employing a polymetal gate stack(W/WNx/Poly-Si). Especially, based on the fully matured production level, DRAM devices gated with polymetal stack were directly compared to those with conventional polycide stack (WSix/Poly-Si) with respect to the impact of gate etch post-cleaning and selective oxidation. Also, we proposed the best solution to overcome the critical issues related to tungsten (W) process, still keeping comparable product performance to conventional polycide gate stack.

Keywords

DRAM chips; etching; integrated circuit metallisation; oxidation; surface cleaning; tungsten; tungsten compounds; W-WN-Si; W/WN/sub x//polysilicon polymetal gate stack; gate etch post-cleaning; high-density DRAM; selective oxidation; tungsten process; volume production; Capacitors; Cleaning; Degradation; Dielectrics; Etching; Oxidation; Production; Random access memory; Research and development; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979584

Filename

979584