DocumentCode
2167651
Title
Polysilicon gate dry etching process optimization in CMOS technologies
Author
Cernica, Ileana ; Dunare, Camelia ; Bocioaca, Liviu ; Moldovan, Carmen ; Buiu, Octavian
Author_Institution
Nat. Inst. of Microtechnol., Bucharest, Romania
Volume
1
fYear
1997
fDate
7-11 Oct 1997
Firstpage
239
Abstract
The dry etch of polysilicon doped with phosphorus using a parallel plate etcher was studied. A standard dry etching process program (used in CMOS 3 μm technology) was compared with a proposed modified program in order to obtain a better anisotropy and lower values for underetching and dimensional dispersion on the wafer
Keywords
CMOS integrated circuits; elemental semiconductors; integrated circuit technology; phosphorus; silicon; sputter etching; 3 mum; CMOS technologies; Si:P; dimensional dispersion; dry etch; dry etching process program; parallel plate etcher; phosphorus; polysilicon; polysilicon gate dry etching process optimization; underetching; Anisotropic magnetoresistance; CMOS process; CMOS technology; Dry etching; Electric variables measurement; Geometry; Measurement standards; Silicon; Standards development; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Conference, 1997. CAS '97 Proceedings., 1997 International
Conference_Location
Sinaia
Print_ISBN
0-7803-3804-9
Type
conf
DOI
10.1109/SMICND.1997.651588
Filename
651588
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