WSI systolic networks: an active silicon circuit board function for ULSI-based parallel computing

The evolution of silicon to 0.25-μm technologies will yield very powerful, single-chip ULSI arrays of high-performance processors and high-capacity wafer-scale memories. The very compact, distributed computing systems which result will require very-high-performance communication networks, scaled to the much smaller size and more monolithic realization of future distributed systems. Multichip systems, using such ULSI processor arrays, suggest wafer-level, monolithic versions of their communication networks, extending current passive `silicon circuit boards´ to silicon wafer area networks. Since VLSI constraints are similar to those of systolic computational arrays, the wafer-level networks might be called systolic communication networks. The author discusses some of the basic design issues facing these communication networks, emphasizing the importance of very high information transfer rates and the objective of achieving virtual, point-to-point interconnections through a switched network