A high-performance DRAM controller based on multi-core system through instruction prefetching

In this paper, we propose a cost-effective way to improve the performance of DRAM based on multi-core system. A novel DRAM controller with instruction prefecthing mechanism is introduced. The controller dynamically selects Open Page(OP) or Close Page(CP) policy by getting some information of future accesses in advance. This DRAM controller with dynamic policy based on instruction prefetching(DP_BIF), can provide DRAM the lowest possible latency without increasing too many areas of chip when compared with the controller only with OP policy or CP policy. The analysis of the simulation results show that the access latency of the DRAM memory can be improved nearly 10.4%, and the throughput of the DRAM is also increased nearly 10.2% by adopting the DP_BIF policy.