DocumentCode
2167825
Title
Dynamic-floating-gate design for output ESD protection in a 0.35-μm CMOS cell library
Author
Ker, Ming-Dou ; Chang, Hun-Hsien ; Wang, Chen-Chia ; Yeng, Horng-Ru ; Tsao, Y.-F.
Author_Institution
VISI Design Div., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
216
Abstract
A dynamic-floating-gate design is proposed to improve ESD robustness of the driving-current-programmable CMOS output buffers in a 0.35 μm CMOS cell library. Through suitable design to dynamically float the gates of the output NMOS/PMOS which are originally unused in a 2 mA output buffer, the ND-mode (PS-mode) ESD level of the 2 mA output buffer can be improved from the original 1.5 kV (1.0 kV) up to greater than 8 kV
Keywords
CMOS integrated circuits; buffer circuits; electrostatic discharge; integrated circuit design; protection; 0.35 micron; 1 to 8 kV; 2 mA; CMOS cell library; CMOS output buffers; ESD robustness improvement; driving-current-programmable buffers; dynamic-floating-gate design; output ESD protection; CMOS technology; Communication industry; Computer aided manufacturing; Electrostatic discharge; Fingers; Libraries; MOS devices; Protection; Robustness; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706880
Filename
706880
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