Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard small outline packages

The electrical models of Bump Chip Carrier (BCC) packages have been established based on the S-parameter measurement. When compared to the standard Thin Shrink Small Outline Packages (TSSOP), BCCs exhibit much smaller parasitics in the equivalent circuits. In the simulation, the insertion and return losses for an arbitrary pair of package leads connected through an on-die 50-ohm line are calculated against frequency. BCCs also show better loss characteristics than TSSOPs over a wide frequency range. By setting a random variable with Gaussian distribution varied within a certain range for each equivalent circuit element of the packages, the Monte Carlo analysis has been performed to study the package effects on a GaAs Heterojunction Bipolar Transistor (HBT). Again, BCCs cause less decrement of HBT´s unity-gain bandwidth than TSSOPs