An area efficient motion estimator for a new block-matching algorithm

In this paper, an area efficient implementation of a motion estimator with full search capability, based on simplified pixel difference classification (PDC) algorithm is presented. Based on a novel approach of matching criteria, enhanced by the fixed pixel threshold technique, the hardware requirement for every single processing element was cut down at a ratio of 30-40% compared with the implementation of conventional algorithms. It is designed for a block size of 16 × 16 pixels, search area -8/7, and can be cascaded by 4 for a search range of -16/15. It allows sequential inputs but performs parallel computations. At 100 MHz clock rate, it needs 2.5 usec to finish calculating one motion vector. Realized by TSMC O.18 μm CMOS technology, it has a core area of 1.01 mm².