Silicon-On-Nothing (SON) applications for Low Power technologies

Author

Monfray, S. ; Boeuf, F. ; Coronel, P. ; Bidal, G. ; Denorme, S. ; Skotnicki, T.

Author_Institution

STMicroelectronics, Crolles

fYear

2008

fDate

2-4 June 2008

Firstpage

1

Lastpage

4

Abstract

The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices. This technology opens a wide range of applications, in particular for the realization of localized single-gate fully depleted transistors on bulk substrates and of double-gate planar devices, co-integrable with conventional bulk devices.

Keywords

CMOS integrated circuits; low-power electronics; SON technology; bulk substrates; double-gate planar devices; end-of-roadmap CMOS; localized single-gate fully depleted transistors; low power technologies; power consumption; silicon-on-nothing applications; sustained mono-Si nanomembranes; ultra-thin body devices; CMOS technology; Capacitance; Delay; Energy consumption; Fabrication; Germanium silicon alloys; High-K gate dielectrics; Nanoscale devices; Silicon germanium; Substrates; Low Power; SiGe; Silicon-On-Nothing; Ultra Thin Body Devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567232

Filename

4567232