Hybrid assembly technology for flip-chip-on-chip (FCOC) using PBGA laminate assembly

Component integration is becoming more and more popular to achieve reduction of space with increasing performance of electronic packages. Dual-Chip-Stack (DCS) is the direct, face to face joining of two (or more) semiconductor devices. It improves significantly component integration by leveraging flip-chip technology processing, standard wirebond packaging and plastic ball grid array (PBGA) processes. High bandwidth interconnections between devices of various process technologies allow the construction of unique, high margin component assemblies. In this paper, the authors describe the assembly development work of a DCS package using a logic device attached to a DRAM device over a PBGA chip-up type carrier. Proposed packaging flow is discussed with process modifications to obtain a robust product. The processes discussed are: flip-chip dicing, device to device joining, wirebond to laminate carrier, and encapsulation (Underfill and Globtop). Some reliability results will also be shown and discussed