CMOS SOI technology for WPAN. Application to 60 GHz LNA

Author

Siligaris, A. ; Mounet, C. ; Reig, B. ; Vincent, P. ; Michel, A.

Author_Institution

CEA/LETI-MINATEC, Grenoble

fYear

2008

fDate

2-4 June 2008

Firstpage

17

Lastpage

20

Abstract

This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it´s possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip passive devices. A short description of the transistor model is also provided. Finally, we discuss the details of the LNA design and show how the simulation results compare to the measurements.

Keywords

CMOS integrated circuits; field effect MIMIC; low noise amplifiers; millimetre wave amplifiers; personal area networks; silicon-on-insulator; CMOS SOI technology; coplanar waveguide modeling; frequency 60 GHz; low noise amplifier; onchip passive devices; Analytical models; CMOS process; CMOS technology; Coplanar waveguides; Electromagnetic modeling; Electromagnetic scattering; Electromagnetic waveguides; Low-noise amplifiers; Microelectronics; Semiconductor device modeling; 60GHz; CMOS; LNA; RF modeling; SOI;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567236

Filename

4567236