Title :
A low power multi-band selector DLL with wide-locking range
Author :
Kuo, Ko-Chi ; Hsu, Yi-Hsi
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung
Abstract :
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The operation frequency can be ranged from 250 MHz to 900 MHz. The static phase error is 6.75 ps and 23.65 ps at 250 MHz and 900 MHz respectively. The power dissipation is 14.5 mW at 900 MHz. The circuit is designed by using TSMC 0.18- mu m single-poly six-metal CMOS process.
Keywords :
CMOS digital integrated circuits; delay lock loops; low-power electronics; TSMC; charge pump; delay-locked loop; frequency 250 MHz to 900 MHz; multiband selector; multicontrol delay line; phase frequency detector; power 14.5 mW; power dissipation; single-poly six-metal CMOS process; size 0.18 mum; start-up circuit; time 23.65 ps; time 6.75 ps; Charge pumps; Circuits; Clocks; Delay lines; Jitter; Phase frequency detector; Phase locked loops; Switches; Voltage control; Voltage-controlled oscillators; Delay lock loop; low power;
Conference_Titel :
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-1810-7
Electronic_ISBN :
978-1-4244-1811-4
DOI :
10.1109/ICICDT.2008.4567238
