DocumentCode :
2168623
Title :
On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing
Author :
Fu, Xiang ; Li, Huawei ; Li, Xiaowei
fYear :
2010
fDate :
1-4 Dec. 2010
Firstpage :
45
Lastpage :
48
Abstract :
Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization criterion. An effective path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS´89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.
Keywords :
automatic test pattern generation; delays; fault simulation; integrated circuit testing; ISCAS´89 benchmark circuit; faster-than-at-speed testing; path delay fault model; single path sensitization criteria; small delay defects; test patterns; testable path selection; Central Processing Unit; Circuit faults; Clocks; Delay; Logic gates; Testing; faster-than at-speed testing; small delay defect; testable path selection;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2010 19th IEEE Asian
Conference_Location :
Shanghai
ISSN :
1081-7735
Print_ISBN :
978-1-4244-8841-4
Type :
conf
DOI :
10.1109/ATS.2010.17
Filename :
5692220
Link To Document :
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