An innovative sub-32nm SRAM current sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

Author

Makosiej, Adam ; Nasalski, Piotr ; Giraud, Bastien ; Vladimirescu, Andrei ; Amara, Amara

Author_Institution

Tech. Univ. of Lodz, Lodz

fYear

2008

fDate

2-4 June 2008

Firstpage

47

Lastpage

50

Abstract

This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease), less power consuming (313% power dissipation decrease) and much more resistant to transistor length (L) (125% gain) and threshold voltage mismatches (Vth) (233% gain).

Keywords

CMOS integrated circuits; SRAM chips; amplifiers; memory architecture; silicon-on-insulator; SOI technology; SRAM current sense amplifier; double-gate CMOS; fully depleted double-gate silicon-on-insulator technology; process variations; self-aligned gates; size 32 nm; transistor mismatch; CMOS process; Capacitance; Integrated circuit technology; MOS devices; Monte Carlo methods; Predictive models; Random access memory; Silicon on insulator technology; Threshold voltage; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567243

Filename

4567243