A simple CMOS delay model for wide applications

Author

Choi, Tae-Yong ; Cho, Won-II ; Kim, Dong-wook

Author_Institution

Dept. of Electron. Mater. Eng., Kwangwoon Univ., Seoul, South Korea

fYear

1996

fDate

18-21 Nov 1996

Firstpage

77

Lastpage

80

Abstract

In this paper, we propose a delay model of CMOS gates for wide application. After introducing a delay model for the CMOS inverter, we develop it for other CMOS gates. In this process, we first remodel the MOSFET and the input signal effectively, and then, we model the MOSFETs in the inverter as a resistor or a current source according to both the input voltage and the output voltage of the inverter such that, when the MOSFET is in the saturation mode, it is modeled as a current source and when it is in the nonsaturation mode, it is modeled as a resistor. The delay model for the CMOS inverter is simply converted for other CMOS gates by minor manipulation. Our model has an accuracy of less than 5% error rate from the SPICE simulation results for the fifteen cascaded CMOS gates of inverter, NAND and NOR

Keywords

CMOS logic circuits; MOSFET; delays; integrated circuit modelling; logic gates; semiconductor device models; CMOS delay model; CMOS gates; CMOS inverter; MOSFET modelling; SPICE simulation; current source; nonsaturation mode; resistor; saturation mode; Circuit simulation; Delay effects; Delay estimation; Integrated circuit modeling; Inverters; MOSFET circuits; Predictive models; Resistors; Semiconductor device modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-3702-6

Type

conf

DOI

10.1109/APCAS.1996.569223

Filename

569223