DocumentCode :
2168855
Title :
Predictive reliability modeling for flipchip interconnect bump extrusion
Author :
Lucero, A.E. ; Dias, Rajen ; Pavey, Thomas
Author_Institution :
Intel Corp., Chandler, AZ, USA
fYear :
2000
fDate :
2000
Firstpage :
619
Lastpage :
623
Abstract :
As next generation packages and package interconnects continue to extend the reliability performance envelope of current designs and materials it is necessary to predict the limitations of the current package and assembly process. The flip-chip, multi-layer Organic Land Grid Array (OLGA) package was developed for the current and future generations of microprocessors and chipsets to be used in applications ranging from servers, desktops and laptops to embedded applications. During normal processing voids in the epoxy underfill between the package and die occur as a result of moisture evaporation and underfill reaction byproducts during dispense and cure. During temperature cycling the lead-tin bump material is extruded into adjacent voids resulting in electrical shorts. As bump pitches are reduced, the risk of bump extrusion failures post temperature cycle increases. A predictive model to assess the potential reliability risk of bump extrusion over the component lifetime was needed prior to process qualification and pitch reduction. Analysis of the experimental data showed that the variables that modulate bump extrusion are void count, bump pitch, bump layout, underfill properties and temperature cycle condition. Using the failure rate and extrusion rate, an empirical reliability model was derived to predict bump extrusion failure rates based on the key variables. Intrinsic and empirical reliability modeling techniques documented in this manuscript can be used to assess the impact of bump pitch reduction, new process evaluations and manufacturing capability planning as related to flip-chip die-package bump extrusion
Keywords :
chip scale packaging; failure analysis; flip-chip devices; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; microprocessor chips; Predictive reliability modeling; bump extrusion; bump extrusion failure rates; bump extrusion failures; bump layout; bump pitch; chipsets; cure; dispense; electrical shorts; empirical reliability model; flip-chip die-package bump extrusion; flipchip interconnect bump extrusion; lead-tin bump material; microprocessors; moisture evaporation; multi-layer Organic Land Grid Array; package interconnects; pitch reduction; predictive model; reliability modeling; reliability performance; reliability risk; temperature cycle; temperature cycle conditio; temperature cycling; underfill properties; underfill reaction byproducts; void count; voids; Assembly; LAN interconnection; Materials reliability; Mesh generation; Microprocessors; Moisture; Packaging; Portable computers; Predictive models; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-5908-9
Type :
conf
DOI :
10.1109/ECTC.2000.853223
Filename :
853223
Link To Document :
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