A 2.4 V, 700 μW, 0.18 mm2 second-order demodulator for high-resolution ΣΔ DACs

This work presents the design and measurement results of a novel second-order demodulator for high-resolution sigma-delta digital to analog converters. The demodulator combines digital to analog converting and second-order lowpass filtering into a single step, therefore, eliminating conventionally required post analog filter. This approach offers a large reduction both in chip size and power consumption. A 14-bit fully differential second-order demodulator has been designed and implemented in a complete 2.4 V cellular baseband chip by using a double-poly and triple-metal 0.5 μm low-power CMOS process. The total active chip area and power consumption of the demodulator are 0.18 mm ² and 700 μW, respectively