Title :
Scalable Two-Transistor Memory (STTM)
Author :
Yi, J.H. ; Kim, W.S. ; Song, S. ; Khang, Y. ; Kim, H.-J. ; Choi, J.H. ; Lim, H.H. ; Lee, N.I. ; Fujihara, K. ; Kang, H.-K. ; Moon, J.T. ; Lee, M.Y.
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd, Gyeonggi, South Korea
Abstract :
A novel memory device called Scalable Two-Transistor Memory (STTM) has been developed. STTM is a floating gate device with the writing mechanism of direct tunneling through the multiple tunnel junction (MTJ). STTM has potential advantages of scalability, high density, high speed, long data retention, low voltage operation, low power consumption, and good endurability. We have fabricated and successfully demonstrated the memory cell operation of the STTM for the first time. The STTM unit cell fabricated using 0.16 /spl mu/m silicon processing showed the writing speed of /spl sim/100 ns and the data retention time of /spl sim/200 sec. with the operation voltages of -5/spl sim/5 V. Also, we developed a novel architecture for the high-density STTM cell array with an unit cell size of 4F/sup 2/ and a process scheme to fabricate it.
Keywords :
high-speed integrated circuits; integrated memory circuits; low-power electronics; tunnelling; -5 to 5 V; 0.16 micron; 100 ns; 200 sec; Si; data retention; direct tunneling; endurability; floating gate device; high-density STTM cell array; high-speed low-voltage operation; multiple tunnel junction; power consumption; scalable two-transistor memory; silicon processing; Computer architecture; Energy consumption; Flash memory; Magnetic tunneling; Nonvolatile memory; Random access memory; Scalability; Silicon; Voltage; Writing;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979632
