Title :
A 60pJ, 3-Clock Rising Time, VTH Loss Compensated Word-Line Booster Circuit for 0.5V Power Supply Embedded/Discrete DRAMs
Author :
Tanakamaru, Shuhei ; Takeuchi, Ken
Author_Institution :
Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo
Abstract :
A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.
Keywords :
DRAM chips; embedded systems; high-speed integrated circuits; low-power electronics; clock rising time; discrete DRAM; embedded DRAM; energy 60 pJ; loss compensated word-line booster circuit; low power high-speed word-line booster; power consumption; voltage 0.5 V; Capacitors; Charge pumps; Circuits; Clocks; Energy consumption; Logic; Parasitic capacitance; Power supplies; Random access memory; Voltage;
Conference_Titel :
Memory Workshop, 2009. IMW '09. IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4244-3762-7
DOI :
10.1109/IMW.2009.5090572
