Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS

Author

Diaz-Madrid, Jose-Angel ; Neubauer, Harald ; Domenech-Asensi, Gines ; Ruiz, Ramon

Author_Institution

IC Design Dept., Fraunhofer Inst. for Integrated Circuits, Erlangen

fYear

2008

fDate

2-4 June 2008

Firstpage

121

Lastpage

124

Abstract

This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for low power dissipation. All analog components of this pipeline ADC are fully differential, as there are dynamic comparators, analog multiplexers and operational amplifiers with gain boosting.

Keywords

CMOS integrated circuits; analogue-digital conversion; network topology; operational amplifiers; CMOS technology; analog multiplexers; gain boosting; operational amplifier topologies; pipeline analog to digital converter; power dissipation; size 0.35 mum; voltage 3.3 TV; Analog-digital conversion; Analytical models; CMOS technology; Capacitors; Operational amplifiers; Pipelines; Power dissipation; Power supplies; Topology; Transient analysis; ADC; CMOS; operational amplifier; pipeline;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567260

Filename

4567260