Title :
Technology development driven by design
Author_Institution :
NXP Semicond. Belgium, Leuven
Abstract :
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
Keywords :
CMOS integrated circuits; circuit optimisation; integrated circuit design; low-power electronics; CMOS integrated circuits; application-optimal technology; buffer cell design; circuit-level optimization; design flow; device characteristics; library design; size 130 nm; technology development; Circuit synthesis; Delay; Design optimization; Libraries; Logic circuits; Logic devices; Paper technology; Space technology; Threshold voltage; Timing; CMOS; EDA; application-specific; library design; low operational power;
Conference_Titel :
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-1810-7
Electronic_ISBN :
978-1-4244-1811-4
DOI :
10.1109/ICICDT.2008.4567262
