VLSI design of a 1.0 GHz 0.6-μm 8-bit CLA using PLA-styled all-N-transistor logic

Author

Chua-Chin Wang ; Tsai, Kun-Chu

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

236

Abstract

A high speed 8-bit carry-lookahead adder (CLA) using two-phase clocking dynamic CMOS logic with modified non-inverting all-N-transistor (ANT) blocks which are arranged in a PLA design style is presented in this paper. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. Detailed simulation results reveal appropriate L/W guidelines for the all-N-transistor (ANT) block design. The analysis of the area (transistor count) tradeoff is also provided in this work. The operating clock frequency is 1.0 GHz while the output of the addition of two 8-bit binary numbers is done in 2 cycles. The proposed design methodology is proved to be also suitable for the long adders, e.g., 64-b adders, while the correct output will be ready in 4 cycles if the 64-b adder is composed of hierarchical nine 8-b CLAs

Keywords

CMOS logic circuits; VLSI; adders; carry logic; logic design; programmable logic arrays; 0.6 micron; 1 GHz; 64 bit; 8 bit; PLA-styled all-N-transistor logic; VLSI design; design methodology; dynamic CMOS logic; high speed carry-lookahead adder; long adders; modified noninverting all-N-transistor blocks; two-phase clocking; Acceleration; CMOS logic circuits; Clocks; Guidelines; Logic design; MOS devices; MOSFETs; Output feedback; Programmable logic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706885

Filename

706885