On-chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter

This paper presents an on-chip jitter measurement technique based on the Vernier ring time-do-digital converter (VRTDC). Vernier delay line is an attractive structure for the implementation of high performance TDC due to its sub-gate-delay resolution and cancellation of the first order process, voltage and temperature (PVT) variations. In order to improve the detectable range, area cost and power consumption of the conventional Vernier delay line TDC, the Vernier ring structure is developed to place two delay lines and comparator chains in ring format for the reuse of hardware, which enables the VR-TDC to achieve a fine resolution without sacrificing detectable range. The build-in coarse and fine interpolations reduce the power and area. This on-chip jitter measurement scheme can measure a large jitter with a fine resolution smaller than 8ps. An exemplary jitter test is given in this paper to demonstrate the capability of the proposed jitter measurement scheme.